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AmdRyzen 5 3450g Firmware

7 matches found

CVE
CVE
added 2022/11/09 9:15 p.m.207 views

CVE-2022-23824

IBPB may not prevent return branch predictions from being specified by pre-IBPB branch targets leading to a potential information disclosure.

5.5CVSS5.6AI score0.00024EPSS
CVE
CVE
added 2022/05/11 5:15 p.m.138 views

CVE-2021-26339

A bug in AMD CPU’s core logic may allow for an attacker, using specific code from an unprivileged VM, to trigger a CPU core hang resulting in a potential denial of service. AMD believes the specific code includes a specific x86 instruction sequence that would not be generated by compilers.

5.5CVSS5.9AI score0.00071EPSS
CVE
CVE
added 2022/05/12 6:16 p.m.79 views

CVE-2021-26351

Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA (Direct Memory Access) read/write from/to invalid DRAM address that could result in denial of service.

5.5CVSS6.3AI score0.00135EPSS
CVE
CVE
added 2023/01/11 8:15 a.m.73 views

CVE-2021-26346

Failure to validate the integer operand in ASP (AMD Secure Processor) bootloader may allow an attacker to introduce an integer overflow in the L2 directory table in SPI flash resulting in a potential denial of service.

5.5CVSS6AI score0.00051EPSS
CVE
CVE
added 2021/11/16 7:15 p.m.65 views

CVE-2021-26336

Insufficient bounds checking in System Management Unit (SMU) may cause invalid memory accesses/updates that could result in SMU hang and subsequent failure to service any further requests from other components.

5.5CVSS6.3AI score0.00135EPSS
CVE
CVE
added 2022/08/10 8:15 p.m.64 views

CVE-2021-46778

Execution unit scheduler contention may lead to a side channel vulnerability found on AMD CPU microarchitectures codenamed “Zen 1”, “Zen 2” and “Zen 3” that use simultaneous multithreading (SMT). By measuring the contention level on scheduler queues an attacker may potentially leak sensitive inform...

5.6CVSS5.7AI score0.00099EPSS
CVE
CVE
added 2021/11/16 7:15 p.m.49 views

CVE-2021-26337

Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA read from invalid DRAM address to SRAM resulting in SMU not servicing further requests.

5.5CVSS6.2AI score0.00107EPSS